EDWARD H. SCHULTZ
3117 Brookfield Dr
Marion Iowa 52302
Technical Design Engineer with extensive experience in JC Semiconductor environment, accepting customer input, and reviewing, running, verifying and releasing data used in product creation. Interact with 17Program Managers, and finance to ensure timely release of products. Pro-active, with excellent communication skills and a focus on increased efficiency with decreased expenses. Known for finalizing data with high quality results. Areas of expertise include:
Release of all CMOS / SOI data to Fabs • Set up Version Assignments
Daily Project Tracking of project PO's • Verify data extents in Version Assignments
Final Review & release of Data from Layout • Generate Reticle plans for projects
Maintained Tape Out log of all data sent • Review & OK Packaging reticle plans
** Project Management I Archiving ** Main contact for CMOS / SOI releases
** In – House EMS Lead Auditor for Company ** ISO 9000, External Audits
TOWER JAZZ SEMICONDUCTOR New Port Beach, Ca 1994-2013
SKYWORKS SEMICONDUCTOR, Cedar Rapids Iowa (June)2014-2016
Senior Principle Design Engineer, Design and Product Quality
Inspected and verified data input from Design Engineers, making sure it passed specifications. Provided foundry locations and entered purchase order numbers and total mask costs into release documents. Interacted across most functional areas to ensure projects were completed correctly and timely so data sent for fabrication to masks encountered no issues.
Reviewed releases to determine the appropriate mask and wafer PO's already exist or have been created in system for use on Wafer sets.
Attached all Reticle & Step plans on documentation that I placed in system for releasing data for fabrication and reticle creation.
Supervised and/or verified all final data for projects. Reviewed List Errors to validate data.
Alerted layout on any incorrect data due to sub micron issues, to be fixed before releasing final data to Fab for mask creation. Consistently achieved data accuracy rate of 99+%
Developed and maintained online Excel spreadsheet that provided tracking visibility to all project that were in progress or in line to be done by designers.
Created 99% of wafer sets for company to run parts in any Fab chosen.
Provided daily follow-up for all customer and internal wafer sets in Fab areas, to make sure there was no stoppage in parts being developed.
Worked with Program managers to assist on correcting any wafer I mask cost issues.
Sent out and requested okay on release permissions from Lead design managers on all projects after attending final design reviews, before releasing data for masks and wafers.
Recognized as "go to" person to solve any work flow issues or problems.
AA, Criminal Justice, Golden West College, Huntington Beach CA 92648 Microchip Layout Design, Orange Coast College Costa Mesa Ca. Com1 1&ti:19- "IT" School,@ Integrated Digital Technologies. Corp.
Fab Process Development of Wafers
SiGi Design, Electrical Development Professional Management Workshops
Certification and Completion of P.O.S.T (996 hours), Orange County Sheriff's Training Facility Reserve Police Officer
TECHNICAL SKILLS Cad Manager / SAP input
Worked 2 years in a Fab to understand processes procedures on wafer sets. Identifying Yield Mask Parameter issues